Controller Area Network (CAN) technology, as its name implied, is the network established among microcontrollers. Like computer networks, it has the similar transmission protocol defined by ISO/OSI (International Standard Protocol/Open System Interconnection) 7-layer model. However, unlike computer networks, it uses a simplified 7-layer model in which only 2 of the lowest stacks were defined, i.e. Data-Link Layer and Physical Layer. This simplification allows the protocol to be more xe2x80x9copenxe2x80x9d than computer networks, i.e. it allows the users freedom to develop their own applications. CAN offers Error Detection/Confinement ability in which the feature is burnt into the silicon during manufacturing. This significantly reduces the burden of the microcontroller in verifying the CAN signal on the bus. The failure node determines itself and retransmit the signal upon detecting the failure in transmission.
CAN was first established for automobiles in mid 1986. The first CAN chip was available in 1987 by Intel. After which, many companies adopted the CAN technology to develop higher level protocols.
CAN consists of a single bit-serial channel for all information. Transmission and reception of data, bit timing and bus arbitration all take place on what is logically a single line. The CAN Physical Layer defines the electrical levels and signaling scheme on the bus, the cable impedance and similar things. The physical layer characteristics are not part of the basic CAN specification. The bus is a single wire plus ground with every node connected to the bus such that every node receives every message. The most common implementation of the physical layer, as defined by ISO 11898, is a two-wire balanced signaling scheme. Several CAN transceiver chips are manufactured by Philips, such as the 82C250 transceiver which implements the physical layer defined by ISO 11898. The ISO 11898 prescribes that the cable impedance be nominally 120 Ohms, but an impedance in the interval of [108 132] Ohms is permitted.
The CAN bus uses Non-Return To Zero (NRZ) with bit-stuffing. There are two different signaling states: dominant and non-dominant. These correspond to certain electrical levels which depend on the physical layer used. The modules are connected to the bus in a wired-AND fashion: if one node is driving the bus to the dominant state, then the whole bus is in that state regardless of the number of nodes transmitting a non-dominate state. This requirement that if one node is driving the bus to the dominant state, then the whole bus is in that state regardless of the number of nodes transmitting a non-dominate state is fundamental to bus arbitration. In particular, bus arbitration for control of the bus takes place while the arbitration field, which is the first field transmitted, is transmitted. If a node, which is sending a non-dominate state, sees that the bus is in the dominate state, it recognizes that another node is transmitting a higher priority message and stops transmitting.
During arbitration, a node transmits its address on the bus. Each node must have a unique address for the arbitration to operate. A common method is to pre-assign addresses to a node either by encoding the address into the device or providing a means of entering an address by using, for example, DIP switches. Setting the DIP switches can be very error prone. Additionally, the bus topology can not be inferred from the addressing.
In order to accomplish the present invention there is provided a wired-and bus emulator interface circuit that has a first bus port having a first input and a first output. There is a second bus port having a second input and a second output and a controller port having a receive, transmit, a first enable and a second enable. The first output outputs a non-dominate state if the first enable is inactive. If the first enable is active, the first output outputs a dominate state if either the transmit or second output is in the dominate state. The second output outputs the non-dominate state if the second enable is inactive. If the second enable is active, the second output outputs the dominate state if either the input or transmit is in the dominate state. The receive outputs the dominate state if either the input, the transmit or the second input is in the dominate state.
There is an alternate embodiment that has a controller port having a receive, a transmit and an enable. There is also a configurable port having an input, an output and a configure. Connecting the configure to a dominate state configures the port as a bus port. Alternatively, connecting the configure to the input configures the port as a second controller port. The receive outputs the dominate state if either the input or transmit is receiving the dominate state. The output outputs the non-dominate state if the enable is inactive. If the port is configured as the bus port, then the output outputs the transmit state if the enable is active. If the port is configured as the second controller port then the output outputs the dominate state if either the input or transmit is receiving the dominate state.
There is yet another alternate embodiment of an interface circuit using a bus port having an input and an output and a controller port having a receive, a transmit and an enable. The receive outputs a dominate state if either the input or transmit is in the dominate state. The output outputs the non-dominate state if the enable is inactive; if the enable is active, the output outputs the transmit state.